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QT200NXg

 
QT200NXg is designed as a Combinational Board Tester with Digital/Analog and Mixed Signal Test capabilities through simple clips and probes or through card edge or as a cluster tester with a special test fixture for up to 256 test pins. In addition, it has the Boundary Scan Test option for virtual pin test where the number of virtual test pins has no physical limit.

Its basic timing unit is 125ns and thus can generate test patterns at 8MHz data rate. The timing units are programmable in 2048 steps allowing accurate pattern timings.

QT200NXg can perform In-Circuit Functional Test, testing individual lCs in In-Circuit or Out-of-Circuit with Pin Status Check & has In-built DRC (Design Rule Checker). QT200NXg utilizes IEEE Standard VHDL language in behavioural description other function of the chip in its library. For Analog / Mixed Signal Devices, Python TD Test languages based scripts are available for stimulus and output evaluation.

Auto compensation is extended for all digital devices (not limiting to SSI/MSI) and thus LSI / VLSI chips can be tested in its In-Circuit configuration without the need to learn from a known good board.

QT200NXgs QSMVI Stimulus for VI Trace can be used from available Standard or from user defined wave pattern, thus not limiting the VI trace to simple sine wave alone. User defined wave pattern can be any mathematical wave shape such as sine, triangle, square, ramp or even arbitrary patterns as desired by user and can be stored in the library for possible re-use. The frequency is fully programmable.

"Best Fit Curve" - an unique feature, where the best drive pattern is automatically suggested to the user for the characteristics of the UUT to increase the fault coverage with Advanced algorithm suggests the failing pin within A device with% probability.

QT200NXg can perform Resistance, Inductance, Capacitance, Voltage and Frequency Measurement along with 3 Channel - 10Mega Sample Scope with Programmable Load and 3 Channel Function Generator. QT200NXg with TestDirector6 Test Sequencer software allows Sequencing of multiple test using combination of isolated device test (IC FT), QSMVI, Measurements, Card Edge Functional Test, Integrated Card Edge +Boundary Scan test (optional), all in one test program.

Test Sequencer Software allows graphical TPS development using JPEG image of the PCB under test, tagging devices and pins. Adding tests to the devices, cluster with just a right click of the mouse. Learn, verify and test options using mouse click on the device location.

Using QT200NXg Card Edge Functional for complex boards with ASICs and BGAs, where no functional data are available. User can generate the test vectors using the graphical waveform editor or Python TD test vector generator, where the primary IO pins can be either physical edge pin, In-Circuit pin or a JTAG Virtual Boundary Scan Pin. User can either learn the expected output from a known good board or define the expected output using graphical waveform editor or simulate the expected output using VHDL Simulation or the Python TD test language with mask / tolerance editing facilities. Test program developed can be used for a device / cluster or a complete PCB.
 
 
 
Features
Maximum Test speed on the pin of DUT up to 8MHz (125 nano seconds) and Programmable Time base
  in 2048 steps
In-Circuit Functional testing of digital, analog and mixed signal Mixed Logic devices
High current rating and five voltage output options for the BUT with latest SMPS module (450 watts)
Qmax Fault Simulation validated vast device library of > 33,000 devices.
QSM VI – a unique analytical tool to troubleshoot faults on Hybrids/Custom ICs as well as ESD damaged
  devices with Auto Best Fit Curve algorithm.
Frequency measurement.
3 channel Digital Oscilloscope and Function Generator.
Clock Terminator feature avoids False Alarm and ensures highest possible fault coverage on a wide 
  range of boards.
In built IEEE Standard VHDL Simulator and Auto In-Circuit compensation.
Dual trace facility for probes and clips
Auto Guarding Guide for Bus based devices and OC / OE Devices.
Logic analyzer waveform display for failure confirmation
Identify Unkown and House Coded devices including LSI devices with advanced foot print match 
  algorithm.
Graphical test program generator for Digital, Analog, Mixed signal devices.
Mixed logic testing through dual palettes
Automatic internal pull-up/down for open collector and open emitter devices
Board Learn/Compare mode results in increased board recovery rate
Optional Circuit Tracer for schematic generation / reverse engineering applications.
Optional IDDE software for easy Device Test Program Generation with Fault coverage report.
Optional Russian Device Library & Military part code library
Automatic Guided Probe Back Tracking for Fault Isolation up to node level.
User defined Error Log reporting, Failure analysis, Statistics and datalog.
Optional Fault Simulation for card Edge Test Program and Library Device Programs.
Optional Fault Dictionary Data Base
Built in self-diagnostic facility for maintenance