Capacitance Voltage (C V) measurements are fundamental for characterizing Metal Oxide Semiconductor (MOS) devices. Most C V work uses high frequencies (100 kHz to 1 MHz), but analyses such as interface trap detection require low frequency, quasistatic techniques. Traditional quasistatic methods that force voltage and measure current work well on silicon (Si) MOS devices. On silicon carbide (SiC) MOS devices, however, the higher capacitance often leads to unstable measurements.

To address this, we introduce the Forced Current Quasistatic C-V Method that improves stability on SiC MOS devices. In this application note, you will learn:

• What Forced Current QSCV is, how it works, and when to use it
• How to run the included tests in the Clarius Software (v14+)
• How Force I QSCV compares with other methods
• How to derive calculations for internal charges on a SiC MOSFET from the forward and reverse C-V sweeps

Download our app note to get started!