Designing high-speed links? As clock and data rates climb, signal integrity is critical for reliable performance.

In this on-demand webinar, Dallas Mohler, Senior Applications Engineer at Tektronix, shares a repeatable workflow to quickly observe and debug real-world SerDes issues—closed eye diagrams, excessive jitter, unexpected noise, and confusing results.

You’ll learn:

• Where and how to probe signals for meaningful insight.
• How to set up clock recovery and when to apply equalization (CTLE/DFE)
• Methodologies to address closed eyes, random vs deterministic jitter, channel & signal path effects, and power rail induced noise

Spot and solve SerDes signal integrity issues fast with fewer re-spins and faster bring-up.