While traditional quasistatic C-V (QSCV) is widely used to study trapped charges in silicon (Si) MOS devices, applying the same method to silicon carbide (SiC) presents new challenges—including higher capacitance and a greater number of traps.

In this on-demand webinar, Mary Anne Tupta and Dr. Alexander Pronin, both Senior Application Engineers at Tektronix, introduce a patent-pending low-frequency C-V technique specifically developed for SiC MOS devices.

The new method uses a forced DC current and extracts the capacitance from the measured voltage and time, using a differential technique. By forcing both a positive and negative current to the gate and plotting the forward and reverse C-V curves, shifts in the voltage and other interesting differences in the curves are observed. Comparing an AC, or high frequency, method to measure the same devices did not show these differences when reversing the polarity of the sweep. The finding suggests that the new technique can extract slow-moving device charges, including trapped charges. The new technique also includes ways to perform an open compensation and correct for leakage current.

Explore this advanced new method and see real-world results.