PCIe^® 6.0 presents numerous challenges due to the transition from NRZ to PAM4 modulation at both the silicon and system levels, requiring new techniques in simulation and post-silicon validation. We are excited to host Monica Olvera from Synopsys and Joey Chiu from Tektronix as they look ahead to PCIe^® 7.0 and its targeted 128 GT/s data rate. They will discuss the pathway to managing the physical layer (PHY) complexities introduced by this new specification revision. Additional topics include 128 GT/s silicon performance, PCIe^®over optical links, and gaining deeper insights into expected signal integrity challenges.

What you will learn: 

• Motivation for PCIe 7.0 Base specification acceleration including the demands of AI hardware clusters
• Latest breakthroughs and remaining challenges of analyzing signal integrity of 128 GT/s
• Silicon performance update at 128 GT/s
• Discussion on PCIe over optical industry work
• How to manage the system needs for this new specification revision

Watch the on-demand webinar to learn more about the latest advancements in simulation, design, and innovative test and measurement methodologies required for this latest inflection point.