| Key product |
| Bus Interface Form factorPCI Express Gen-3 x8 Reconfigurable FPGA FPGA KU11P LUTs 298,560 DSP48 slices (25 × 18 multiplier) 2,928 Embedded Block RAM 21 Mb Timebase reference sources PXI Express 100 MHz (PXIe_CLK100) Data transfers DMA, interrupts, programmed I/O Embedded UltraRAM™ 22 Mb Number of DMA channels 60 Onboard DRAM 4 GB (2 banks of 2 GB) DRAM clock rate 1064 MHz Physical bus width 32 bit LabVIEW FPGA DRAM clock rate 267 MHz LabVIEW FPGA DRAM bus width 256 bit per bank Maximum theoretical data rate 17 GB/s (8.5 GB/s per bank) Serial I/O Characteristics |
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