Key product
Digital I/O
Number of connectors4

Number of channels per connector

32

Maximum frequency

80 MHz

Compatibility

LVTTL, LVCMOS

Logic family

Software-selectable

Default software setting

3.3 V

Maximum DC output current per channel
Source

4.0 mA

Sink

4.0 mA

Output impedance

50 Ω

Power-on state

Programmable, by line

Protection

±20 V, single line

Digital I/O voltage selection

Programmable, per connector, and defined at compilation (not run-time configurable)

Direction control of digital I/O channels

Per channel

Minimum I/O pulse width

6.25 ns

Minimum sampling period

5 ns

External Clock
Direction

Input into device

Maximum input leakage

±15 µA

Characteristic impedance

50 Ω

Power-on state

Tristated

Minimum input

-0.3 V

Maximum input

3.6 V

Logic level

Inherited from programmed digital voltage selection per connector

Maximum input frequency

80 MHz

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